Important RGPV Question
EC-303 (DSD) Digital System Design
III Sem, EC
UNIT-1 : Number Systems
Q.1) Simplify the following using quine-mccluskey method?
f(w,x,y,z) =Σ m(0, 1,3,9, 10, 12, 13, 14)+ Σ d (2,5,6, 11)
(RGPV June 2023)
Q.2) State and prove Demorgan’s theorem.
OR
What is De-Morgan’s theorem ? Simplify the given expression using De-Morgan’s theorem.
(RGPV June 2023, Dec 2020, Nov 2018, RGPV Nov 2019)
Q.3) Convert the following binary numbers into decimal, octal and hexadecimal:
i) 111100001101
ii) 111. 0111
(RGPV June 2023)
Q.4) What is basic logic gates? Explain with truth table and diagram.
(RGPV June 2020)
Q.5) Simplify the Boolean function using K-map
F(w,x,y,z)= Σ (0,1,2,4,5,6,8,9,12,13,14)
(RGPV June 2020)
Q.6) Define Parity generator and half adder. Design 4-bit magnitude comparator.
(RGPV June 2020)
Q.7) Convert the following.
i) (312.4)5 to Decimal.
ii) Binary code 10110 to Gray code.
(RGPV June 2020)
Q.8) Find the binary equivalent of 4557.
(RGPV Dec 2020,May 2019)
Q.9) Find the decimal equivalent of 100110111.
(RGPV Dec 2020)
Q.10) Convert the following:
i) (10011100010)2 =( )10
ii) 1111.1011 = ( )â‚‚
iii) (67)10 = ( )2
iv) (68.87)10 = ( )2
v) (444)10=( )2
(RGPV Dec 2020, May 2019)
Q.11) With the help of suitable example explain BCD, Excess 3 and Gray code.
(RGPV Dec 2020)
Q.12) Minimize the following using Karnaugh Map:
F(A, B, C, D) = Σ (0,5,7,9,11,13)
(RGPV Dec 2020, May 2019)
Q.13) Convert the following.
i) (1.375)10 to Binary
ii) Gray code 1101 to Binary code
(RGPV Dec 2020)
Q.14) What is universal gate? Why multiplexer is called universal gate?
(RGPV Dec 2020,Nov 2019)
Q.15) Write short note Quine McCluskey Method
(RGPV Dec 2020,May 2019)
Q.16) Explain the process of conversion from Octal to Hexadecimal System.
(RGPV May 2019)
Q.17) Minimize the following using Karnaugh map-
F(A, B, C, D) = Σ (0, 4, 8, 12).
(RGPV Nov 2018)
Q.18) Minimize the given expression using K-map.
(RGPV Nov 2019)
Q.19) Differentiate between analog and digital circuits.
OR
Explain some of the differences between analog and digital circuits.
(RGPV Nov 2018,Dec 2020, RGPV May 2019)
Q.20) Convert the following (i) (48.625)10=( )2;
(ii) Divide (IEC87)16 by (45)16.
(RGPV June 2014)
Q.21) Convert the number (210.25)10 to base 2,8.
(RGPV June 2015)
Q.22) Add and subtract octal numbers 360 and 715.
(RGPV Dec 2015)
Q.23) Convert the following-
(i) (1111)2=( )10
(ii) (10010.1011)2=()10
(iii) (23)10=( )2
(iv) (5.5)10=( )2
(v) (47.6)10=( )2
(RGPV Nov 2018)
Q.24) Subtract (1010)2, from (1000)2; using I’s and 2’s complement method.
(RGPV Dec 2014)
Q.25) Explain the difference between a weighted and non-weighted code with example.
(RGPV June 2015)
Q.26) With the help of suitable example explain BCD, Excess-3 and gray codes.
(RGPV Nov 2018)
Q.27) Explain the following classification of binary codes- (i) Weighted codes (ii) Non-weighted codes (iii) Reflective codes (iv) Alphanumeric codes.
(RGPV Dec 2017)
Q.28) Convert 10111011 in binary into its equivalent Gray code.
(RGPV June 2015)
Q.29) (i) Convert binary (10110)2 to Gray code.
(ii) The seven bit Hamming code as received is 0010001. Assuming that even parity has been used, check is it correct? If not find correct code.
(RGPV June 2014)
Q.30) What are logic gates?
(RGPV June 2015)
Q.31) Show that a positive logic AND gate is a negative logic OR gate and vice versa.
(RGPV June 2017)
Q.32) Explain the difference between positive and negative logic giving an example of each as applied to voltage levels.
(RGPV Nov 2018, Dec 2020)
Q.33) What is universal gate?
OR
What are universal gates? Explain with example.
OR
What are universal gates? Why are they called so?
(RGPV June 2014, RGPV Dec 2014, RGPV Dec 2015)
Q.34) Define NAND and NOR gates and give their truth tables. Write down the Boolean expressions for the output of each gate.
(RGPV Nov 2018,May 2019)
Q.35) What is universal gate? Implement AND, OR and NOT gates using NAND gates and NOR gates.
(RGPV Dec 2017)
Q.36) Discuss AND, OR, X-OR and X-NOR gates.
(RGPV June 2011)
Q.37) Draw the logic diagram of EX-NOR gate using only NOR gates.
(RGPV Dec 2015)
Q.38) Write short note on exclusive OR gate.
(RGPV Dec 2017)
Q.39) Implement EX-OR gate using NOR gates.
(RGPV June 2015)
Q.40) Draw the diagram of digital circuit for F(a, b, c) = AB+ BC+ CD using NAND to NAND logic.
(RGPV Nov 2018)
UNIT-2 : Combinational Logic Circuits
Q.1) Design one full adder using two half adders.
(RGPV June 2023)
Q.2) Design and explain a 4-bit priority encoder.
(RGPV June 2023)
Q.3) What is Full subtractor? Write its truth table and design the logic circuit.
(RGPV June 2020)
Q.4) Design 4-bit carry look ahead adder.
(RGPV June 2020)
Q.5) What is full adder? Write its truth table and design the logic circuit.
(RGPV Nov 2019)
Q.6) Explain full adder.
OR
Draw the truth table and logic diagram of full adder.
OR
Design a full adder circuit and write its truth table. Implement it with logic gates.
(RGPV Dec 2013, RGPV Dec 2015, RGPV Dec 2017)
Q.7) Explain the working of half adder.
OR
Draw the circuit diagram for half adder.
OR
Design a half adder.
(RGPV Dec 2013, RGPV June 2015, RGPV Dec 2014)
Q.8) Implement a full adder circuit with a (3 to 8) decoder and two OR gates.
OR
Implement a full adder circuit with a decoder and two OR gates.
(RGPV Dec 2017, RGPV June 2014)
Q.9) Implement the full-subtractor with two half-subtractor and an OR gate.
OR
Design a full subtractor circuit.
OR
Explain the construction of full subtractor using half subtractor.
(RGPV June 2005, 2010, 2015,2017, RGPV June 2012, RGPV Dec 2016)
Q.10) Design a full subtractor circuit using decoder and OR gates.
(RGPV Dec 2015)
Q.11) Draw the logic diagram of look-ahead carry generator and explain its working.
OR
Explain the operation of look-ahead carry generator.
OR
Discuss/Explain the working of look ahead carry generator.
OR
What is look ahead carry generator? Explain with logic diagram.
OR
Design and explain the working of look ahead carry generator.
OR
Discuss logic circuit of look-ahead carry generator.
(RGPV Dec 2008, 2015, RGPV June 2007, 2008, 2010, RGPV Dec 2012, June 2015, RGPV June 2014, RGPV Dec 2014, RGPV June 2017)
Q.12) Design and explain the working of BCD adder.
OR
Draw the logic diagram of BCD adder and explain its working.
(RGPV Dec 2014, RGPV Dec 2015)
Q.13) Implement the following Boolean function using 4:1 multiplexer using A and B variables to the selection lines. F(A, B, C) = 2 Σm (1, 4, 5, 7)
(RGPV Dec 2015)
Q.14) Explain the working of encoders.
OR
Write short note on encoder.
(RGPV Dec 2013, RGPV June 2015)
Q.15) Draw the logic diagram of priority encoder and explain its working.
(RGPV Dec 2015)
Q.16) Write short note on the parity generator
(RGPV Dec 2016)
UNIT-3 : Sequential Logic Design
Q.1) Write a short notes on JK flip-flop
(RGPV June 2023)
Q.2) Design a modulo-6 counter which counts in the sequence 0,1,2,3,4,5,0, 1……. The counter counts the clock pulses if it’s enable input is equal to I, using D flip-flop.
(RGPV June 2023)
Q.3) Explain Tand D Flip-Flop.
(RGPV June 2020)
Q.4) Explain the designing of synchronous FSM.
(RGPV Dec 2020, May 2019)
Q.5) Explain the working of T flip-flop. How to convert a J-K flip- flop into T flip-flop.
(RGPV Nov 2018)
Q.6) Draw the logic diagram of a master slave D-flip-flop. Use NAND gates.
(RGPV June 2017)
Q.7) Differentiate combinational and sequential circuits. Give suitable examples for each class.
(RGPV Dec 2017)
Q.8) What do you mean by flip-flops? Define D flip-flop with diagrams and tables.
(RGPV Dec 2017)
Q.9) Discuss logic diagram, graphical symbol, characteristic table and characteristic equation of J-K flip-flop.
(RGPV June 2017)
Q.10) Write short note on the T flip-flop.
(RGPV Dec 2016)
Q.11) What is master-slave flip-flop? How race around condition is avoided in master-slave flip-flop?
(RGPV Dec 2016)
Q.12) Convert J-K flip-flop to S-R flip-flop.
(RGPV Dec 2016, Nov 2019)
UNIT 4 : Registers & Counters
Q.1) Design and explain the working of 4-bit ring counter.
(RGPV June 2023)
Q.2) Design asynchronous 4-bit up/down counter using JK flip-flop.
(RGPV June 2023)
Q.3) What do you mean by Flip-Flop? Define JK Flip-Flop with diagram and tables.
(RGPV June 2020)
Q.4) Write about shift counters and universal shift registers.
(RGPV June 2020)
Q.5) Explain Universal Shift registers with example.
(RGPV May 2019)
Q.6) What is synchronous and Asynchronous counter?
(RGPV Nov 2019)
Q.7) Write about Ring counter and Universal shift registers.
(RGPV Nov 2019)
Q.8) Write short note on ripple counter.
(RGPV Nov 2018)
Q.9) Write short note on universal shift registers.
(RGPV Nov 2018)
Q.10) Write short note on sequence generators.
(RGPV Nov 2018)
Q.11) Draw the diagram of 4-bit ripple counter and explain with suitable waveform.
OR
Design a serial counter.
(RGPV Dec 2016, RGPV June 2017)
Q.12) Explain the working of four bit synchronous counter.
OR
Write short note on synchronous counter.
(RGPV Dec 2014, RGPV Nov 2018)
Q.13) Explain difference between the synchronous and asynchronous counters.
OR
Differentiate between synchronous and asynchronous counters.
(RGPV June 2023, RGPV June 2005, 2012, Dec 2017)
Q.14) Design a BCD counter with J-K flip-flops.
(RGPV June 2017)
Q.15) What do you mean by shift registers? Design a shift left register of 4 bits.
(RGPV Dec 2017)
Q.16) Draw and explain the logic diagram of 4-bit register with parallel load.
(RGPV June 2017)
Q.17) Explain the difference between synchronous and asynchronous counter. Why is synchronous counters faster than asynchronous counter?
(RGPV Dec 2016)
Q.18) Write short note on the Modulo-N counter.
(RGPV Dec 2016)
Q.19) Design a 4-bit synchronous up counter using J-K flip-flops.
(RGPV Dec 2015)
Q.20) What is shift register? Mention some application of shift register.
(RGPV June 2015)
Q.21) Design a mod-12 binary counter using J-K flip-flop.
(RGPV June 2015)
UNIT-5 : Logic Families & Semiconductor Memories
Q.1) Draw and explain Tri-state TTLNAND gate
(RGPV June 2023)
Q.2) Explain in detail FPGA with suitable block diagram.
(RGPV June 2023)
Q.3) Draw the diagram of TTL NAND gate and explain its working.
(RGPV June 2020)
Q.4) Write short notes on
a) Excess-3 code
b) CMOS family
c) Pulse train generator
(RGPV June 2020, RGPV June, Dec 2020, May 2019)
Q.5) Draw the diagram of Tri-state TTL and explain its working.
(RGPV Dec 2020, Nov 2019)
Q.6) Draw the circuit of basic ECL inverter and explain its operations.
(RGPV Dec 2020)
Q.7) Discuss Resistor Transistor Logic (RTL)? Explain how it performs the NOR logic function?
(RGPV Dec 2020)
Q.8) Give a brief classification of CMOS families.
(RGPV May 2019)
Q.9) Write short note on FPGA.
(RGPV Nov 2018)
Q.10) Discuss resistor transistor logic (RTL). Explain how it performs the NOR logic function?
(RGPV Nov 2018)
Q.11) Draw the circuit of basic ECL inverter and explain its operations.
(RGPV Nov 2018)
Q.12) Write short note on ECL family.
OR
Write short note on ECL.
(RGPV June 2007, Dec 2010, 2017, RGPV June 2017)
Q.13) Differentiate TTL and DTL logic families. Define fan-out.
(RGPV Dec 2017)
Q.14) Define the terms PROM, EEPROM, EAPROM.
(RGPV Dec 2017)
Q.15) Design a combinational circuit that accepts a three bit number and generates an output binary number equal to the square of the input number.
(RGPV June 2017)
Q.16) Differentiate the dynamic and static RAM.
(RGPV Dec 2017
Q.17) Write short note on PLA.
(RGPV Dec 2005, June 2007, Dec 2010, June 2012, 2017, Dec 2017)
Q.18) What are the major types of semiconductor memories?
OR
Give broad classification of semiconductor memories.
(RGPV June 2017, RGPV June 2015)
Q.19) Write short note on TTL circuits.
OR
Draw the diagram of TTL NAND gate and explain its working.
(RGPV June 2008, 2017, RGPV Dec 2016)
Q.20) Draw and explain the VI characteristics of CMOS inverter.
(RGPV Dec 2016)
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