Important RGPV Question
EC 504 (B) Computer System Organisation
V Sem, EC
UNIT 1 COMPUTER BASICS
Q.1 What are the different addressing modes of computer? (RGPV Dec 2020)
Q.2 Draw the basic architecture of CPU. (RGPV Dec 2020)
Q.3 Explain: (RGPV Dec 2020)
- i) Data movement and Data manipulation
- ii) System Bus
Q.4 What is micro-instruction formats? (RGPV Dec 2020)
Q.5 What task performs by following machine code? Assume initially: R1 = x, R2 = y, R3 = 0, R4 = 0
INC R1 #RESULT =x+1
COPY R3 #R3x+1
INC R3
COPY R3
MULT R1, R3 #RESULT = x* (x+2)
COPY R3
ADD R2, R2 #RESULT-2*Y
COPY R4
(RGPV Nov 2022)
Q.6 Consider the basic computer registers connected to a common bus system, if the memory size is 256 k word each of length 32 bits, and the instruction format has three parts: an Indirect address bit (I), the op-code part and the address part for this system perform the following:
- i) What is the number of bits of the address bus?
- ii) What is the number of memory reference instructions; register reference instructions?
(RGPV Nov 2022)
Q.7 Explain how a typical DMA controller can be interfaced to CPU or microprocessor with suitable example. (RGPV Nov 2022)
Q.8 An I/O device transfers 10 MB/s of data into the memory of a processor over the I/O bus, which has a total bandwidth of 100 MB/s. The 10MB of data is transferred as 2500 independent pages, each of which is 4kB in length. If the processor operates at 200 MHz, it takes 1000 cycles to initiate a DMA transaction and 1500 cycles to respond to the device’s interrupt when the DMA transfer completes, what fraction of the CPU’s time is spent handling the data transfer with DMA? (RGPV Nov 2022)
UNIT 2 CONTROL UNIT ORGANIZATION
Q.1 Explain hard wired control unit. (RGPV Dec 2020)
Q.2 Describe the arithmetic operations performed by ALU. (RGPV Dec 2020)
Q.3 Write short notes on. (RGPV Dec 2020)
- a) Arithmetic pipeline
- b) Memory registers
- c) Accumulator
- d) ALU
Q.4 Draw and explain the flowchart of floating point addition process. (RGPV Nov 2022)
Q.5 Explain the differences between hardwired control and micro programmed control? Is it possible to have a hardwired control associated with a control memory? (RGPV Nov 2022)
Q.6 Find a method of encoding the micro instructions described by the following table so that the minimum number of control bits is used and all inherent parallelism among the micro-operations is preserved. (RGPV Nov 2022)
Q.7 With a neat sketch explain the micro programmed control organization. (RGPV Nov 2022)
Q.8 A hardwired CPU uses 10 control signals $1 to $10 in various time steps T1 to T5 to implement 4 instructions Il to 14 as shown below.
Find out the Boolean Expressions represent the circuit for generating control signals S5, S6 and S10 respectively? [(Ij+Ik) Tn, indicates that the control signal should be generated in time step Tn if the instruction being executed is Ij or Ik] (RGPV Nov 2022)
UNIT 3 INPUT OUTPUT ORGANIZATION
Q.1 What is the need for the interrupts? (RGPV Dec 2020)
Q.2 What is simplex and duplex data transfer? (RGPV Dec 2020)
Q.3 Briefly describe I/O interface. (RGPV Dec 2020)
Q.4 Draw flow chart and Explain Program Controlled I/O technique of data transfer between the CPU and I/O device. (RGPV Nov 2022)
Q.5 The original I/O bus operated at 33 MHz and transferred 32 bits of data at a time. If the hard disks attached to the I/ O bus could deliver a maximum of 40 MB per sec, is it possible to use a video card that needed 128 MB/sec of bandwidth to meet the demands of an application? Justify your answer. (RGPV Nov 2022)
UNIT 4 MEMORY ORGANIZATION
Q.1 Explain memory management hardware. (RGPV Dec 2020)
Q.2 What are the different types of memory? (RGPV Dec 2020)
Q.3 Explain memory mapping in computers. (RGPV Dec 2020)
Q.4 What do you mean by virtual memory? Discuss how paging helps in implementing virtual memory. (RGPV Nov 2022)
Q.5 Explain the different types of mapping procedures in the organization of cache memory with diagram. (RGPV Nov 2022)
Q.6 Suppose a 32-bit byte-addressable CPU accesses memory in the following order: 433, 435, 536, 535, 443, 444, 551, 538, 539, 553. Assume that we have 4 cache blocks. Initially the cache is empty. (1 word 4 bytes) and 12 bits memory addresses are in hex decimal. (RGPV Nov 2022)
i) If the cache is direct-mapped, what is the total number of misses? Assume I block is 1 word. (Ignore the tag field and other bits.)
ii) If the cache is 2-way set associative with LRU replacement policy, what is the total number of misses? Assume block isl words. (Ignore the tag field and other bits.)
iii) If the cache is fully associative with FIFO replacement policy, what is the total number of misses? Assume I block is 1 word. (Ignore the tag field and other bits)
UNIT 5 MULTIPROCESSORS
Q.1 What is pipelining and vector process? (RGPV Dec 2020)
Q.2 Describe vector and array processors. (RGPV Dec 2020)
Q.3 Cache memory 16KB instruction cache and 16KB data cache. (RGPV Nov 2022)
Hit cycle: 1, Miss cycle: 50
75% read access and 25% write access
Read miss rate 0.64%, Write miss rate=6.47%
What is the Average memory access time (AMAT)?
Q.4 Formulate a four segment instruction pipeline for a computer. Specify the operation to be performed in each segment. (RGPV Nov 2022)
— Best of Luck for Exam —
